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856 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hs-80c86rh radiation hardened 16-bit cmos microprocessor description the intersil hs-80c86rh high performance radiation hardened 16-bit cmos cpu is manufactured using a hardened ?eld, self aligned silicon gate cmos process. two modes of operation, minimum for small systems and maximum for larger applications such as multiprocessing, allow user con?guration to achieve the highest performance level. industry standard operation allows use of existing nmos 8086 hardware and software designs. features ? radiation hardened - latch up free epl-cmos - total dose >100k rad (si) - transient upset >10 8 rad (si)/s ? low power operation - iccsb = 500 m a (max) - iccop = 12ma/mhz (max) ? pin compatible with nmos 8086 and intersil 80c86 ? completely static design dc to 5mhz ? 1mb direct memory addressing capability ? 24 operand addressing modes ? bit, byte, word, and block move operations ? 8-bit and 16-bit signed/unsigned arithmetic - binary or decimal - multiply and divide ? bus-hold circuitry eliminates pull-up resistors for cmos designs ? hardened field, self-aligned, junction-isolated cmos process ? single 5v power supply ? military temperature range -35 o c to +125 o c ? minimum let for single event upset -6mev/mg/cm 2 (typ) september 1995 ordering information part number temperature range screening level package HS1-80C86RH-8 -35 o c to +125 o c intersil class b equivalent 40 lead braze seal dip hs1-80c86rh-q -35 o c to +125 o c intersil class s equivalent 40 lead braze seal dip hs9-80c86rh-8 -35 o c to +125 o c intersil class b equivalent 42 lead braze seal flatpack hs9-80c86rh-q -35 o c to +125 o c intersil class s equivalent 42 lead braze seal flatpack hs9-80c86rh-sample 25 o c sample 42 lead braze seal flatpack hs1-80c86rh-sample 25 o c sample 40 lead braze seal dip hs9-80c86rh-proto -35 o c to +125 o c prototype 42 lead braze seal flatpack hs1-80c86rh-proto -35 o c to +125 o c prototype 40 lead braze seal dip spec number 518055 file number 3035.1
857 spec number 518055 hs-80c86rh pinouts hs-80c86rh 40 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835, cdip2-t40 top view hs-80c86rh 42 lead ceramic metal seal flatpack package (flatpack) intersil outline k42.a top view ad16/s3 ad15 a19/s6 rd bhe/s7 rq/ gt1 rq/ gt0 vdd mn/ mx lock s2 s1 s0 qs0 qs1 test ready reset ad6 ad5 ad12 ad11 ad10 ad9 ad8 ad7 gnd gnd ad14 ad4 ad3 ad2 ad1 ad0 nmi intr clk ad13 a18/s5 a17/s4 (hlda) (hold) ( wr) (m/ io) (dt/ r) ( den) (ale) ( int a) max min 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 nc ad15 a18/s5 rq/ gt0 rd vdd bhe/s7 rq/ gt1 lock s2 s1 s0 qs0 qs1 test ready a16/s3 reset ad6 ad5 ad12 ad11 ad10 ad9 ad8 ad7 gnd ad14 ad4 ad3 ad2 ad1 ad0 intr clk gnd ad13 nc nmi mn/ mx a19/s6 a17/s4 max min (hlda) (hold) ( wr) (m/ io) (dt/ r) ( den) (ale) ( int a) 42 41 40 39 38 37 36 35 34 33 32 31 2 3 4 5 6 7 8 9 11 1 30 29 28 27 26 25 24 23 22 12 13 14 15 16 17 18 19 20 21 10
858 spec number 518055 hs-80c86rh functional diagram register file execution unit control and timing instruction queue 6-byte flags 16-bit alu bus interface unit 16 4 qs0, qs1 s2, s1, s0 2 4 3 gnd vdd clk reset ready bus interface unit relocation register file 3 a19/s6 a16/s3 int a, rd, wr dt/ r, den, ale, m/ io bhe/s7 2 segment registers and instruction pointer (5 words) data pointer and index regs (8 words) test intr nmi hlda hold rq/ gt 0, 1 lock mn/ mx 3 es cs ss ds ip ah bh ch dh al bl cl dl sp bp si di arithmetic/ logic unit b+bus c-bus execution unit interface unit bus queue instruction stream byte execution unit control system flags memory interface a-bus ad15-ad0
859 spec number 518055 hs-80c86rh pin description symbol pin number type description the following pin function descriptions are for hs-80c86rh systems in either minimum or maximum mode. the local bus in these de- scriptions is the direct multiplexed bus interface connection to the hs-80c86rh (without regard to additional bus buffers). ad15-ad0 2-16, 39 i/o address data bus: these lines constitute the time multiplexed memory/io address (t1) and data (t2, t3, tw, t4) bus. ao is analogous to bhe for the lower byte of the data bus, pins d7-d0. it is low during t1 when a byte is to be transferred on the lower portion of the bus in memory or i/o operations. eight-bit oriented devices tied to the lower half would normally use ad0 to condition chip select functions (see bhe). these lines are active high and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus hold ac- knowledge or grant sequence. a19/s6 a18/s5 a17/s4 a16/s3 35-38 o address/status: during t1, these are the four most significant address lines for memory operations. during i/o operations these lines are low. during memory and i/o operations, status information is available on these lines during t2, t3, tw, t4. s6 is always zero. the status of the interrupt enable flag bit (s5) is updated at the beginning of each clk cycle. s4 and s3 are encoded. this information indicates which segment register is presently being used for data accessing. these lines are held at high impedance to the last valid logic level during local bus hold acknowl- edge or grant sequence. s4 s3 0 0 extra data 0 1 stack 1 0 code or none 1 1 data bhe/s7 34 o bus high enable/status: during t1 the bus high enable signal ( bhe) should be used to enable data onto the most significant half of the data bus, pins d15-d8. eight bit oriented devices tied to the upper half of the bus would normally use bhe to condition chip select functions. bhe is low during t1 for read, write, and interrupt acknowledge cycles when a byte is to be trans- ferred on the high portion of the bus. the s7 status information is available during t2, t3 and t4. the signal is active low, and is held at high impedance to the last valid logic level during interrupt acknowledge and local bus hold acknowledge or grant sequence; it is low during t1 for the first interrupt acknowledge cycle. bhe a0 0 0 whole word 0 1 upper byte from/to odd address 1 0 lower byte from/to even address 1 1 none rd 32 o read: read strobe indicates that the processor is performing a memory or i/o read cycle, de- pending on the state of the m/ io or s2 pin. this signal is used to read devices which reside on the hs-80c86rh local bus. rd is active low during t2, t3 and tw of any read cycle, and is guaranteed to remain high in t2 until the 80c86 local bus has floated. this line is held at a high impedance logic one state during hold acknowledge or grant se- quence. ready 22 i ready: is the acknowledgment from the addressed memory or i/o device that will complete the data transfer. the rdy signal from memory or i/o is synchronized by the hs-82c85rh clock generator to form ready. this signal is active high. the hs-80c86rh ready input is not synchronized. correct operation is not guaranteed if the setup and hold times are not met. intr 18 i interrupt request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge op- eration. if so, an interrupt service routine is called via an interrupt vector lookup table located in system memory. intr is internally synchronized and can be internally masked by software re- setting the interrupt enable bit. this signal is active high. test 23 i test: input is examined by the wait instruction. if the test input is low execution continues, otherwise the processor waits in an idle state. this input is synchronized internally during each clock cycle on the leading edge of clk. nmi 17 i non-maskable interrupt: is an edge triggered input which causes a type 2 interrupt. an interrupt service routine is called via an interrupt vector lookup table located in system memory. nmi is not maskable internally by software. a transition from low to high initiates the interrupt at the end of the current instruction. this input is internally synchronized.
860 spec number 518055 hs-80c86rh reset 21 i reset: causes the processor to immediately terminate its present activity. the signal must change from low to high and remain active high for at least 4 clk cycles. it restarts execution, as described in the instruction set description, when reset returns low. reset is internally synchronized. clk 19 i clock: provides the basic timing for the processor and bus controller. it is asymmetric with a 33% duty cycle to provide optimized internal timing. vdd 40 vdd: +5v power supply pin. a 0.1 m f capacitor between pins 20 and 40 is recommended for decoupling. gnd 1, 20 gnd: ground. note: both must be connected. a 0. 1m f capacitor between pins 1 and 20 is recommended for decoupling. mn/ mx 33 i minimum/ maximum: indicates what mode the processor is to operate in. the two modes are discussed in the following sections. the following pin function descriptions are for the hs-80c86rh system in maximum mode (i.e., mn/ mx = gnd). only the pin functions which are unique to maximum mode are described below. s0, s1, s2 26-28 o status: is active during t4, t1 and t2 and is returned to the passive state (1,1,1) during t3 or during tw when ready is high. this status is used by the 82c88 bus controller to generate all memory and i/o access control signals. any change by s2, s1, or s0 during t4 is used to indicate the beginning of a bus cycle, and the return to the passive state in t3 or tw is used to indicate the end of a bus cycle. these status lines are encoded. these signals are held at a high impedance logic one state during grant sequence. s2 s1 s0 0 0 0 interrupt acknowledge 0 0 1 read i/o port 0 1 0 write i/o port 0 1 1 halt 1 0 0 code access 1 0 1 read memory 1 1 0 write memory 1 1 1 passive rq/ gt0 rq/ gt1 31, 30 i/o request/grant: pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. each pin is bidirectional with rq/gt0 hav- ing higher priority than rq/gt1. rq/gt has an internal pull-up bus hold device so it may be left unconnected. the request/grant sequence is as follows (see rq/gt sequence timing.) 1. a pulse of 1 clk wide from another local bus master indicates a local bus request (hold) to the hs-80c86rh (pulse 1). 2. during a t4 or t1 clock cycle, a pulse 1 clk wide from the hs-80c86rh to the requesting master (pulse 2) indicates that the hs-80c86rh has allowed the local bus to float and that it will enter the grant sequence state at the next clk. the cpus bus interface unit is dis- connected logically from the local bus during grant sequence. 3. a pulse 1 clk wide from the requesting master indicates to the hs-80c86rh (pulse 3) that the hold request is about to end and that the hs-80c86rh can reclaim the local bus at the next clk. the cpu then enters t4 (or t1 if no bus cycles pending). each master-master exchange of the local bus is a sequence of 3 pulses. there must be one idle clk cycle after each bus exchange. pulses are active low. if the request is made while the cpu is performing a memory cycle, it will release the local bus during t4 of the cycle when all the following conditions are met: 1. request occurs on or before t2. 2. current cycle is not the low byte of a word (on an odd address). 3. current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. a locked instruction is not currently executing. if the local bus is idle when the request is made the two possible events will follow: 1. local bus will be released during the next cycle. 2. a memory cycle will start within 3 clks. now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. pin description (continued) symbol pin number type description
861 spec number 518055 hs-80c86rh lock 29 o lock: output indicates that other system bus masters are not to gain control of the system bus while lock is active low. the lock signal is activated by the lock pre?x instruction and re- mains active until the completion of the next instruction. this signal is active low, and is held at a high impedance logic one state during grant sequence. in max mode, lock is automatically generated during t2 of the ?rst int a cycle and removed during t2 of the second int a cycle. qs1, qs0 24, 25 o queue status: the queue status is valid during the clk cycle after which the queue operation is performed. qs1 and qs2 provide status to allow external tracking of the internal hs-80c86rh instruction queue. note that qs1, qs0 never become high impedance. qs1 qs0 0 0 no operation 0 1 first byte of opcode from queue 1 0 empty the queue 1 1 subsequent byte from queue the following pin function descriptions are for the hs-80c86rh in minimum mode (i.e. mn/ mx = vdd). only the pin functions which are unique to minimum mode are described; all other pin functions are as described below. m/ io 28 o status line: logically equivalent to s2 in the maximum mode. it is used to distinguish a mem- ory access from an i/o access. m/ io becomes valid in the t4 preceding a bus cycle and remains valid until the final t4 of the cycle (m = high, io = low). m/ io is held to a high impedance logic zero during local bus hold acknowledge. wr 29 o write: indicates that the processor is performing a write memory or write i/o cycle, depending on the state of the m/ io signal. wr is active for t2, t3 and tw of any write cycle. it is active low, and is held to high impedance logic one during local bus hold acknowledge. int a 24 o interrupt acknowledge: is used as a read strobe for interrupt acknowledge cycles. it is active low during t2, t3 and tw of each interrupt acknowledge cycle. note that int a is never floated. ale 25 o address latch enable: is provided by the processor to latch the address into the 82c82 latch. it is a high pulse active during clock low of tl of any bus cycle. note that ale is never floated. dt/ r 27 o data transmit/receive: is needed in a minimum system that desires to use a data bus transceiver. it is used to control the direction of data flow through the transceiver. logically, dt/ r is equivalent to s1 in maximum mode, and its timing is the same as for m/ io (t = hlgh, r = low). dt/ r is held to a high impedance logic one during local bus hold acknowledge. den 26 o data enable: provided as an output enable fora bus transceiver in a minimum system which uses the transceiver. den is active low during each memory and i/o access and for int a cycles. for a read or int a cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is active from the beginning of t2 until the middle of t4. den is held to a high impedance logic one during local bus hold acknowledge. hold hlda 31 30 i o hold: indicates that another master is requesting a local bus hold. to be a acknowledged, hold must be active high. the processor receiving the hold will issue a hold acknowledge (hlda) in the middle of a t4 or t1 clock cycle. simultaneously with the issuance of hlda, the processor will float the local bus and control lines. after hold is detected as being low, the processor will lower hlda, and when the processor needs to run another cycle, it will again drive the local bus and control lines. hold is not an asynchronous input. external synchronization should be provided if the system cannot otherwise guarantee the setup time. pin description (continued) symbol pin number type description
862 spec number 518055 speci?cations hs-80c86rh absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0v input or output voltage applied for all grades . . . . . . . . . . . . . . . . . .vss-0.3v to vdd+0.3v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c typical derating factor . . . . . . . . . . . 12ma/mhz increase in iddop esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sbdip package . . . . . . . . . . . . . . . . . . . . 40.0 o c/w 8.6 o c/w ceramic flatpack package . . . . . . . . . . . 72.1 o c/w 9.7 o c/w maximum package power dissipation at +125 o c ambient sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mw/ o c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . 13.9mw/ o c gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating supply voltage range (vdd) . . . . . . . +4.75v to +5.25v operating temperature range (t a ) . . . . . . . . . . . . -35 o c to +125 o c input low voltage (vil) . . . . . . . . . . . . . . . . . . . . . . . . . 0v to +0.8v input high voltage (vih) . . . . . . . . . . . . . . . . . . . . . . . . 3.5v to vdd clock input low voltage (vilc) . . . . . . . . . . . . . . . . . . 0.0v to 0.8v clk and mn/ mx input high (vihc) . . . . . . . . . . vdd - 0.8v to vdd table 1. dc electrical performance characteristics parameters symbol conditions group a subgroups temperature limits units min max ttl high level output voltage voh1 vdd = 4.75v, io = -2.5ma vin = 0v or vdd 1, 2, 3 -35 o c, +25 o c, +125 o c 3.0 - v cmos high level output voltage voh2 vdd = 4.75v, io = -100 m a vin = 0v or vdd 1, 2, 3 -35 o c, +25 o c, +125 o c vdd - 0.4v -v low level output voltage vol vdd = 4.75v, io = +2.5ma vin = 0v or vdd 1, 2, 3 -35 o c, +25 o c, +125 o c - 0.4 v input leakage current iih or iil vdd = 5.25v vin = 0v or vdd pins: 17-19, 21-23, 33 1, 2, 3 -35 o c, +25 o c, +125 o c -1.0 1.0 m a output leakage current iozl or iozh vdd = 5.25v vin = 0v or vdd pins: 2-16, 26-29, 32, 34-39 1, 2, 3 -35 o c, +25 o c, +125 o c -10 10 m a input current bus hold high ibhh vdd = 4.75v and 5.25v vin = 3.0v (note 1) pins: 2-16, 26-32, 34-39 1, 2, 3 -35 o c, +25 o c, +125 o c -600 -40 m a input current bus hold low ibhl vdd = 4.75v and 5.25v vin = 0.8v (note 2) pins: 2-16, 34-39 1, 2, 3 -35 o c, +25 o c, +125 o c 40 600 m a standby power supply current iddsb vdd = 5.25v, vin = gnd or vdd, io = 0ma (note 3) 1, 2, 3 -35 o c, +25 o c, +125 o c - 500 m a operating power supply current iddop vdd = 5.25v, vin = gnd or vdd, io = 0ma, f = 1mhz 1, 2, 3 -35 o c, +25 o c, +125 o c - 12 ma/mhz functional tests ft vdd = 4.75v and 5.25v, vin = gnd or vdd, f = 1mhz 7, 8a, 8b -35 o c, +25 o c, +125 o c -- - noise immunity functional tests fn vdd = 4.75v and 5.25v, vin = gnd or 3.5v and vdd = 4.5v, vin = 0.8v or vdd (note 4) 7, 8a, 8b -35 o c, +25 o c, +125 o c -- - notes: 1. ibhh should be measured after raising vin to vdd and then lowering to 3.0v. 2. ibhl should be measured after lowering vin to vss and then raising to 0.8v. 3. iddsb tested during clock high time after halt instruction executed. 4. clk and mn/ mx input high (vihc) = vdd -0.8
863 spec number 518055 speci?cations hs-80c86rh table 2a. ac electrical performance characteristics (min mode) acs tested at worst case vdd, acs guaranteed over full operating speci?cations. parameters symbol conditions group a subgroups temperature limits units min max clk cycle period tclcl vdd = 4.75v vdd = 5.25v 9, 10, 11 -35 o c, +25 o c, +125 o c 200 - ns clk low time tclch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 118 - ns clk high time tchcl vdd = 4.75v vdd = 5.25v 9, 10, 11 -35 o c, +25 o c, +125 o c 69 - ns data in setup time tdvcl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns data in hold time tcldx1 vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 - ns ready setup time into 80c86rh tryhch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 113 - ns ready hold time into 80c86rh tchryx vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns ready inactive to clk (note 2) trylcl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c -8 - ns hold setup time thvch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 35 - ns intr, nmi, test/setup time tinvch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns min mode timing responses (cl = 100pf) address valid delay tclav vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns ale width tlhll vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c tclch - 20 -ns ale active delay tcllh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c -80ns ale inactive delay tchll vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c -85ns address hold time to ale inactive tllax vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c tchcl - 10 -ns control active delay 1 tcvctv vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns control active delay 2 tchctv vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns control inactive delay tcvctx vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns rd active delay tclrl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 165 ns rd inactive delay tclrh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 150 ns rd inactive to next address active trhav vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c tclcl - 45 -ns hlda valid delay tclhav vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 160 ns
864 spec number 518055 speci?cations hs-80c86rh rd width trlrh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 2tclcl - 75 -ns wr width twlwh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 2tclcl - 60 -ns address valid to ale low tavll vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c tclch - 60 -ns output rise time toloh vdd = 4.75v from 0.8v to 2.0v 9, 10, 11 -35 o c, +25 o c, +125 o c -20ns output fall time tohol vdd = 4.75v from 2.0v to 0.8v 9, 10, 11 -35 o c, +25 o c, +125 o c -20ns notes: 1. setup requirement for asynchronous signal only to guarantee recognition at next clk. 2. applies only to t2 state (8ns into t3). table 2b. ac electrical performance characteristics (max mode) acs tested at worst case vdd, acs guaranteed over full operating speci?cations. parameters symbol conditions group a subgroups temperature limits units min max timing requirements clk cycle period tclcl vdd = 4.75v vdd = 5.25v 9, 10, 11 -35 o c, +25 o c, +125 o c 200 - ns clk low time tclch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 118 - ns clk high time tchcl vdd = 4.75v vdd = 5.25v 9, 10, 11 -35 o c, +25 o c, +125 o c 69 - ns data in setup time tdvcl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns data in hold time tcldx1 vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 - ns ready setup time into 80c86rh tryhch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 113 - ns ready hold time into 80c86rh tchryx vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns ready inactive to clk (note 2) trylcl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c -8 - ns intr, nmi, test/setup time tinvch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns rq/ gt setup time tgvch vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 30 - ns rq hold time into hs-80c86rh (note 3) tchgx vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 40 tchcl + 10 ns max mode timing responses (cl = 100pf) ready active to status passive (notes 2 and 4) tryhsh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c - 110 ns status active delay tchsv vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns table 2a. ac electrical performance characteristics (min mode) (continued) acs tested at worst case vdd, acs guaranteed over full operating speci?cations. parameters symbol conditions group a subgroups temperature limits units min max
865 spec number 518055 speci?cations hs-80c86rh status inactive delay (note 4) tclsh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 130 ns address valid delay tclav vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 110 ns rd active delay tclrl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 165 ns rd inactive delay tclrh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 10 150 ns rd inactive to next address active trhav vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c tclcl - 45 -ns gt active delay tclgl vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 085ns gt inactive delay tclgh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 085ns rd width trlrh vdd = 4.75v 9, 10, 11 -35 o c, +25 o c, +125 o c 2tclcl - 75 -ns output rise time toloh vdd = 4.75v from 0.8v to 2.0v 9, 10, 11 -35 o c, +25 o c, +125 o c -20ns output fall time tohol vdd = 4.75v from 2.0v to 0.8v 9, 10, 11 -35 o c, +25 o c, +125 o c -20ns notes: 1. setup requirement for asynchronous signal only to guarantee recognition at next clk. 2. applies only to t2 state (8ns into t3). 3. the hs-80c86rh actively pulls the rq/gt pin to a logic one on the following clock low time. 4. status lines return to their inactive (logic one) state after clk goes low and ready goes high. table 3a. electrical performance characteristics parameters symbol conditions temperature limits units min max input capacitance cin vdd = open, f = 1mhz (note 1) t a = +25 o c - 15 pf output capacitance cout vdd = open, f = 1mhz (note 1) t a = +25 o c - 15 pf i/o capacitance ci/o vdd = open, f = 1mhz (note 1) t a = +25 o c - 20 pf timing requirements clk rise time tch1ch2 vdd = 4.75v and 5.25v min and max mode from 1.0v to 3.5v -35 o c < t a < +125 o c - 15 ns clk fall time tcl2cl1 vdd = 4.75v and 5.25v min and max mode from 3.5v to 1.0v -35 o c < t a < +125 o c - 15 ns input rise time tilih vdd = 4.75v and 5.25v min and max mode from 0.8v to 2.0v -35 o c < t a < +125 o c - 25 ns input fall time tihil vdd = 4.75v and 5.25v min and max mode from 2.0v to 0.8v -35 o c < t a < +125 o c - 25 ns table 2b. ac electrical performance characteristics (max mode) (continued) acs tested at worst case vdd, acs guaranteed over full operating speci?cations. parameters symbol conditions group a subgroups temperature limits units min max
866 spec number 518055 speci?cations hs-80c86rh timing responses address hold time tclax vdd = 4.75v and 5.25v min and max mode -35 o c < t a < +125 o c10 - ns address float delay (note 2) tclaz vdd = 4.75v and 5.25v min and max mode -35 o c < t a < +125 o c tclax 80 ns data valid delay tcldv vdd = 4.75v and 5.25v min and max mode -35 o c < t a < +125 o c 10 110 ns data hold time tcldx2 vdd = 4.75v and 5.25v min and max mode -35 o c < t a < +125 o c10 - ns data hold time after wr twhdx vdd = 4.75v and 5.25v min mode -35 o c < t a < +125 o c tclcl - 30 - ns status float delay (note 2) tchsz vdd = 4.75v and 5.25v max mode -35 o c < t a < +125 o c - 80 ns address float to read active (note 2) tazrl vdd = 4.75v and 5.25v min and max mode -35 o c < t a < +125 o c0 - ns notes: 1. all measurements referenced to device ground. 2. output drivers disabled. bus hold circuitry still active. 3. the parameters are controlled via design or process parameters and are not directly tested. these parameters are characterize d upon initial design release and upon design changes which would affect these characteristics. table 3b. electrical performance characteristics timing signals at hs-82c85rh or 82c88 for reference only. parameters symbol conditions temperature limits units min max rdy setup time into hs-82c85rh (note 1) tr1vcl min and max mode -35 o c < t a < +125 o c35 - ns rdy hold time into hs-82c85rh (note 1) tclr1x min and max mode -35 o c < t a < +125 o c0 - ns command active delay tclml max mode only -35 o c < t a < +125 o c 5 35 ns command inactive tclmh max mode only -35 o c < t a < +125 o c 5 35 ns status valid to ale high tsvlh max mode only -35 o c < t a < +125 o c - 20 ns status valid to mce high tsvmch max mode only -35 o c < t a < +125 o c - 30 ns clk low to ale valid tcllh max mode only -35 o c < t a < +125 o c - 20 ns clk low to mce high tclmch max mode only -35 o c < t a < +125 o c - 25 ns ale inactive delay tchll max mode only -35 o c < t a < +125 o c 4 18 ns mce inactive delay tclmcl max mode only -35 o c < t a < +125 o c - 15 ns control active delay tcvnv max mode only -35 o c < t a < +125 o c 5 45 ns control inactive delay tcvnx max mode only -35 o c < t a < +125 o c1045 ns note: 1. setup requirement for asynchronous signal only to guarantee recognition at next clk. table 4. post 100k rad electrical performance characteristics note: see 25 o c limits in table 1 and table 2 for post rad limits (subgroups 1, 7 and 9). table 3a. electrical performance characteristics (continued) parameters symbol conditions temperature limits units min max
867 spec number 518055 speci?cations hs-80c86rh table 5. burn-in delta parameters (+25 o c) parameter symbol delta limits standby power supply current iddsb 100 m a output leakage current iozl, iozh 2 m a input leakage current iih, iil 200na low level output voltage vol 80mv ttl high level output voltage voh1 600mv cmos high level output voltage voh2 150mv table 6. applicable subgroups conformance group mil-std-883 method group a subgroups tested for -q recorded for -q tested for -8 recorded for -8 initial test 100%/5004 1, 7, 9 1 (note 2) 1, 7, 9 interim test 1 100%/5004 1, 7, 9, d 1, d (note 2) 1, 7, 9 pda 1 100%/5004 1, 7, d 1, 7 interim test 2 100%/5004 1, 7, 9, d 1, d (note 2) n/a pda 2 100%/5004 1, 7, d n/a final test 100%/5004 2, 3, 8a, 8b, 10, 11 2, 3, 8a, 8b, 10, 11 group a (note 1) sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 1, 2, 3, 7, 8a, 8b, 9, 10, 11 subgroup b5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 1, 2, 3 (note 2) n/a subgroup b6 sample 5005 1, 7, 9 n/a group c sample 5005 n/a n/a 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group d sample 5005 1, 7, 9 1, 7, 9 group e, subgroup 2 sample 5005 1, 7, 9 1, 7, 9 notes: 1. alternate group a testing in accordance with mil-std-883 method 5005 may be exercised. 2. table 5 parameters only. functional description static operation all hs-80c86rh circuitry is of static design. internal registers, counters and latches are static and require no refresh as with dynamic circuit design. this eliminates the minimum operating frequency restriction placed on other microprocessors. the cmos hs-80c86rh can operate from dc to 5mhz. the processor clock may be stopped in either state (high/low) and held there inde?nitely. this type of operation is especially useful for system debug or power critical applications. the hs-80c86rh can be single stepped using only the cpu clock. this state can be maintained as long as is necessary. single step clock operation allows simple interface circuitry to provide critical information for bringing up your system. static design also allows very low frequency operation (down to dc). in a power critical situation, this can provide extremely low power operation since hs-80c86rh power dissipation is directly related to operating frequency. as the system frequency is reduced, so is the operating power until, ultimately, at a dc input frequency, the hs-80c86rh power requirement is the standby current, (500 m a maximum). internal architecture the internal functions of the hs-80c86rh processor are partitioned logically into two processing units. the ?rst is the bus interface unit (biu) and the second is the execution unit (eu) as shown in the cpu functional diagram. these units can interact directly but for the most part perform as separate asynchronous operational processors. the bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. this unit also provides the basic bus control. the overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.
868 spec number 518055 hs-80c86rh the instruction stream queuing mechanism allows the blu to keep the memory utilized very ef?ciently. whenever there is space for at least 2 bytes in the queue, the blu will attempt a word fetch memory cycle. this greatly reduces dead-time on the memory bus. the queue acts as a first-in-first-out (flfo) buffer, from which the eu extracts instruction bytes as required. if the queue is empty (following a branch instruction, for example), the ?rst byte into the queue immediately becomes available to the eu. the execution unit receives pre-fetched instructions from the blu queue and provides un-relocated operand addresses to the blu. memory operands are passed through the blu for processing by the eu, which passes results to the blu for storage. memory organization the processor provides a 20-bit address to memory, which locates the byte being referenced. the memory is organized as a linear array of up to 1 million bytes, addressed as 00000(h) to fffff(h). the memory is logically divided into code, data, extra and stack segments of up to 64k bytes each, with each segment falling on 16 byte boundaries. (see figure 1). figure 1. hs-80c86rh memory organization all memory references are made relative to base addresses contained in high speed segment registers. the segment types were chosen based on the addressing needs of programs. the segment register to be selected is automatically chosen according to the speci?c rules of table 7. all information in one segment type share the same logical attributes (e.g. code or data). by structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster and more structured. (see table 7). word (16-bit) operands can be located on even or odd address boundaries and are thus not constrained to even boundaries as is the case in many 16-bit computers. for address and data operands, the least signi?cant byte of the word is stored in the lower valued address location and the most signi?cant byte in the next higher address location. the blu automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. except for the performance penalty, this double access is transparent to the software. the performance penalty does not occur for instruction fetches; only word operands. physically, the memory is organized as a high bank (d15- d6) and a low bank (d7-d0) of 512k bytes addressed in par- allel by the processors address lines. byte data with even addresses is transferred on the d7-d0 bus lines while odd addressed byte data (a0 high) is transferred on the d15-d6 bus lines. the processor provides two enable signals, bhe and a0, to selectively allow reading from or writing into either an odd byte location, even byte location, or both. the instruction stream is fetched from memory as words and is addressed internally by the processor at the byte level as necessary. in referencing word data, the blu requires one or two memory cycles depending on whether the starting byte of the word is on an even or odd address, respectively. con- sequently, in referencing word operands performance can be optimized by locating data on even address boundaries. this is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multi- plexing. certain locations in memory are reserved for speci?c cpu operations (see figure 2). locations from address ffff0h through fffffh are reserved for operations including a jump to the initial program loading routine. following reset, the cpu will always begin execution at location ffff0h where the jump must be located. locations 00000h through 003ffh are reserved for interrupt operations. each of the 256 possible interrupt service routines is accessed through its own pair of 16-bit pointers - segment address pointer and offset address pointer. the ?rst pointer, used as the offset address, is loaded into the 1p and the second pointer, which designates the base address is loaded into the cs. at this point program control is transferred to the interrupt routine. the pointer elements are assumed to have been stored at the respective places in reserved memory prior to occur- rence of interrupts. table 7. type of memory reference default segment base alternate segment base offset instruction fetch cs none ip stack operation ss none sp variable (except following) ds cs, es, ss effective address string source ds cs, es, ss si string destination es none di bp used as base register ss cs, ds, es effective address segment register file cs ss ds es 64k bit + offset fffffh code segment xxxxoh stack segment data segment extra segment 00000h
869 spec number 518055 hs-80c86rh figure 2. reserved memory locations minimum and maximum operation modes the requirements for supporting minimum and maximum hs-80c86rh systems are suf?ciently different that they cannot be met ef?ciently using 40 uniquely de?ned pins. consequently, the hs-80c86rh is equipped with a strap pin (mn/ mx) which de?nes the system con?guration. the de?ni- tion of a certain subset of the pins changes, dependent on the condition of the strap pin. when the mn/ mx pin is strapped to gnd, the hs-80c86rh de?nes pins 24 through 31 and 34 in maximum mode. when the mn/ mx pin is strapped to vdd, the hs-80c86rh generates bus control signals itself on pins 24 through 31 and 34. bus operation the hs-80c86rh has a combined address and data bus commonly referred to as a time multiplexed bus. this tech- nique provides the most ef?cient use of pins on the proces- sor while permitting the use of a standard 40-lead package. this local bus can be buffered directly and used throughout the system with address latching provided on memory and i/o modules. in addition, the bus can also be demultiplexed at the processor with a single set of 82c82 latches if a stan- dard non-multiplexed bus is desired for the system. each processor bus cycle consists of at least four clk cy- cles. these are referred to as t1, t2, t3 and t4 (see figure 3). the address is emitted from the processor during t1 and data transfer occurs on the bus during t3 and t4. t2 is used primarily for changing the direction of the bus during read operations. in the event that a not ready indication is given by the addressed device, wait states (tw) are inserted between t3 and t4. each inserted wait state is the same duration as a clk cycle. idle periods occur between hs-80c86rh driven bus cycles whenever the processor performs internal processing. during t1 of any bus cycle, the ale (address latch ena- ble) signal is emitted (by either the processor or the 82c88 bus controller, depending on the mn/ mx strap). at the trail- ing edge of this pulse, a valid address and certain status information for the cycle may be latched. reset bootstrap program jump interrupt pointer for type 255 interrupt pointer for type 1 interrupt pointer for type 0 fffffh ffffoh 3ffh 3fch 7h 4h 3h 0h status bits s0, s1 and s2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to table 8. status bits s3 through s7 are time multiplexed with high order address bits and the bhe signal, and are therefore valid during t2 through t4. s3 and s4 indicate which seg- ment register (see instruction set description) was used for this bus cycle in forming the address, according to table 9. s5 is a re?ection of the psw interrupt enable bit. s6 is always zero and s7 is a spare status bit. i/o addressing in the hs-80c86rh, i/o operations can address up to a maximum of 64k i/o byte registers or 32k i/o word regis- ters. the i/o address appears in the same format as the memory address on bus lines a15-a0. the address lines a19-a16 are zero in i/o operations. the variable i/o instruc- tions which use register dx as a pointer have full address capability while the direct i/o instructions directly address one or two of the 256 i/o byte locations in page 0 of the i/o address space. i/o ports are addressed in the same manner as memory locations. even addressed bytes are transferred on the d7- d0 bus lines and odd addressed bytes on d15-d8. care must be taken to ensure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even. table 8. s2 s1 s0 characteristics 0 0 0 interrupt acknowledge 0 0 1 read i/o port 0 1 0 write i/o port 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 passive (no bus cycle) table 9. s4 s3 characteristics 0 (low) 0 alternate data (extra segment) 0 1 stack 1 (high) 0 code or none 1 1 data
870 spec number 518055 hs-80c86rh figure 3. basic system timing (4 + nwait) = tcy t1 t2 t3 t4 twait t1 t2 t3 t4 twait (4 + nwait) = tcy goes inactive in the state just prior to t4 bhe, a19-a16 s7-s3 a15-a0 d15-d0 valid a15-a0 data out (d15-d0) ready ready wait wait memory access time addr/ status clk ale s2- s0 addr/data rd, int a ready dt/ r den wp
871 spec number 518055 hs-80c86rh external interface processor reset and lnitialization processor initialization or start up is accomplished with acti- vation (high) of the reset pin. the hs-80c86rh reset is required to be high for greater than 4 clk cycles. the hs-80c86rh will terminate operations on the high-going edge of reset and will remain dormant as long as reset is high. the low-going transition of reset triggers an internal reset sequence for approximately 7 clk cycles. after this interval, the hs-80c86rh operates normally beginning with the instruction in absolute location ffffoh. (see figure 2). the reset input is internally synchronized to the processor clock. at initialization, the high-to-low transition of reset must occur no sooner than 50 m s (or 4 clk cycles, whichever is greater) after power-up, to allow complete initialization of the hs-80c86rh. nml will not be recognized prior to the second clock cycle fol- lowing the end of reset. if nmi is asserted sooner than 9 clk cycles after the end of reset, the processor may execute one instruction before responding to the interrupt. bus hold circuitry to avoid high current conditions caused by ?oating inputs to cmos devices and to eliminate need for pull- up/down resis- tors, bus-hold circuitry has been used on the hs-80c86rh pins 2-16, 26-32 and 34-39. (see figure 4a and 4b). these circuits will maintain the last valid logic state if no driving source is present (i.e. an unconnected pin or a driving source which goes to a high impedance state). to overdrive the bus hold circuits, an external driver must be capable of supplying approximately 400 m a minimum sink or source cur- rent at valid input voltage levels. since this bus hold cir- cuitry is active and not a resistive type element, the associated power supply current is negligible and power dis- sipation is signi?cantly reduced when compared to the use of passive pull-up resistors. figure 4a. bus hold circuitry pin 2-16, 34-39 figure 4b. bus hold circuitry pin 26-32 interrupt operations interrupt operations fall into two classes: software or hard- ware initiated. the software initiated interrupts and software aspects of hardware interrupts are speci?ed in the instruc- tion set description. hardware interrupts can be classi?ed as non-maskable or maskable. interrupts result in a transfer of control to a new program location. a 256-element table containing address pointers to the interrupt service routine locations resides in absolute locations 0 through 3ffh, which are reserved for this pur- pose. each element in the table is 4 bytes in size and corre- sponds to an interrupt type. an interrupting device supplies an 8-bit type number during the interrupt acknowledge sequence, which is used to vector through the appropriate element to the interrupt service routine location. all ?ags and both the code segment and instruction pointer register are saved as part of the int a sequence. these are restored upon execution of an interrupt return (lret) instruction. non-maskable interrupt (nmi) the processor provides a single non-maskable interrupt pin (nml) which has higher priority than the maskable interrupt request pin (intr). a typical use would be to activate a power failure routine. the nml is edge-triggered on a low- to-high transition. the activation of this pin causes a type 2 interrupt. nml is required to have a duration in the high state of greater than 2 clk cycles, but is not required to be synchro- nized to the clock. any positive transition of nml is latched on-chip and will be serviced at the end of the current instruc- tion or between whole moves of a block-type instruction. worst case response to nml would be for multiply, divide, and variable shift instructions. there is no speci?cation on the occurrence of the low-going edge; it may occur before, during or after the servicing of nml. another positive edge triggers another response if it occurs after the start of the nml procedure. the signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses. maskable interrupt (intr) the hs-80c86rh provides a single interrupt request input (intr) which can be masked internally by software with the resetting of the interrupt enable ?ag (if) status bit. the inter- rupt request signal is level triggered. it is internally synchro- nized during each clock cycle on the high-going edge of clk. to be responded to, intr must be present (high) dur- ing the clock period preceding the end of the current instruc- tion or the end of a whole move for a block- type instruction. intr may be removed anytime after the falling edge of the ?rst int a signal. during the interrupt response sequence fur- ther interrupts are disabled. the enable bit is reset as part of the response to any interrupt (intr, nml, software interrupt or single-step), although the flags register which is auto- matically pushed onto the stack re?ects the state of the pro- cessor prior to the interrupt. until the old flags register is restored the enable bit will be zero unless speci?cally set by an instruction. output driver input buffer input protection circuitry bond pa d external pin output driver input buffer input protection circuitry bond pa d external pin p vcc
872 spec number 518055 hs-80c86rh during the response sequence (figure 5) the processor exe- cutes two successive (back-to-back) interrupt acknowledge cycles. the hs-80c86rh emits the lock signal (max mode only) from t2 of the ?rst bus cycle until t2 of the sec- ond. a local bus hold request will not be honored until the end of the second bus cycle. in the second bus cycle, a byte is supplied to the hs-80c86rh by the hs-82c89arh inter- rupt controller, which identi?es the source (type) of the inter- rupt. this byte is multiplied by four and used as a pointer into the interrupt vector lookup table. an intr signal left high will be continually responded to within the limitations of the enable bit and sample period. the interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags. figure 5. interrupt acknowledge sequence halt when a software halt instruction is executed the pro- ces- sor indicates that it is entering the halt state in one of two ways depending upon which mode is strapped. in minimum mode, the processor issues one ale with no qualifying bus control signals. in maximum mode the processor issues appropriate halt status on s2, s1, s0 and the 82c88 bus controller issues one ale. the hs-80c86rh will not leave the halt state when a local bus hold is entered while in halt. in this case, the processor reissues the halt indi- cator at the end of the local bus hold. an nml or interrupt request (when interrupts enabled) or reset will force the hs-80c86rh out of the halt state. read/modify/write (semaphore) operations via loc k the lock status information is provided by the processor when consecutive bus cycles are required during the execu- tion of an instruction. this gives the processor the capability of performing read/modify/write operations on memory (via the exchange register with memory instruction, for exam- ple) without another system bus master receiving interven- ing memory cycles. this is useful in multiprocessor system con?gurations to accomplish test and set lock operations. the lock signal is activated (forced low) in the clock cycle following decoding of the software lock pre?x instruction. it is deactivated at the end of the last bus cycle of the instruction following the lock pre?x instruction. while lock is active a request on a rq/ gt pin will be recorded and then honored at the end of the lock. external synchronization via test as an alternative to interrupts, the hs-80c86rh provides a single software-testable input pin ( test). this input is uti- lized by executing a wait instruction. the single wait instruction is repeatedly executed until the test input goes active (low). the execution of wait does not consume bus cycles once the queue is full. if a local bus request occurs during wait execution, the hs- 80c86rh three-states all output drivers while inputs and i/o pins are held at valid logic levels by internal bus-hold circuits. if interrupts are enabled, the hs-80c86rh will recognize interrupts and process them when it regains control of the bus. the wait instruction is then refetched, and reexecuted. basic system timing typical system con?gurations for the processor operating in minimum mode and in maximum mode are shown in figures 6a and 6b, respectively. in minimum mode, the mn/ mx pin is strapped to vdd and the processor emits bus control sig- nals (e.g. rd, wr, etc.) directly. in maximum mode, the mn/ mx pin is strapped to gnd and the processor emits coded status information which the 82c88 bus controller used to generate multibus? compatible bus control sig- nals. figure 3 shows the signal timing relationships. table 10. hs-80c86rh register model system timing - minimum system the read cycle begins in t1 with the assertion of the address latch enable (ale) signal. the trailing (low-going) edge of this signal is used to latch the address information, which is valid on the address/data bus (ad0-ad15) at this time, into the 82c82 latches. the bhe and a0 signals address the low, high or both bytes. from t1 to t4 the m/ io signal indicates a memory or i/o operation. at t2, the address is removed from the address/data bus and the bus is held at the last valid logic state by internal bus hold devices. the read control signal is also asserted at t2. the read ( rd) signal causes the addressed device to enable its data bus drivers to the local bus. some time later, valid data ale lock int a ad0- float type ad15 t1 t2 t3 t4 ti t1 t2 t3 t4 vector ah bh ch dh sp bp si di ip flagsh cs ds ss es al bl cl dl flagsl accumulator base count data stack pointer base pointer source index destination index instruction pointer status flags code segment data segment stack segment extra segment ax bx cx dx multibus? is an intel trademark
873 spec number 518055 hs-80c86rh will be available on the bus and the addressed device will drive the ready line high. when the processor returns the read signal to a high level, the addressed device will three- state its bus drivers. if a transceiver is required to buffer the hs-80c86rh local bus, signals dt/r and den are provided by the hs-80c86rh. a write cycle also begins with the assertion of ale and the emission of the address. the m/ io signal is again asserted to indicate a memory or i/o write operation. in t2, immed- iately following the address emission, the processor emits the data to be written into the addressed location. this data remains valid until at least the middle of t4. during t2, t3 and tw, the processor asserts the write control signal. the write ( wr) signal becomes active at the beginning of t2 as opposed to the read which is delayed somewhat into t2 to provide time for output drivers to become inactive. the bhe and a0 signals are used to select the proper byte(s) of the memory/io word to be read or written accord- ing to table 11. i/o ports are addressed in the same manner as memory location. even addressed bytes are transferred on the d7-d0 bus lines and odd address bytes on d15-d6. the basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge sig- nal ( int a) is asserted in place of the read ( rd) signal and the address bus is held at the last valid logic state by internal bus hold devices. (see figure 4). in the second of two suc- cessive int a cycles a byte of information is read from the data bus (d7-d0) as supplied by the interrupt system logic (i.e. hs-82cs9arh priority interrupt controller). this byte identi?es the source (type) of the interrupt. it is multiplied by four and used as a pointer into an interrupt vector iookup table, as described earlier. table 11. bhe a0 characteristics 0 0 whole word 0 1 upper byte from/to odd address 1 0 lower byte from/to even address 1 1 none bus timing - medium and large size systems for medium complexity systems the mn/ mx pin is connected to gnd and the 82c88 bus controller is added to the system as well as three 82c82 latches for latching the system address, and a transceiver to allow for bus loading greater than the hs-80c86rh is capable of handling. bus control signals are generated by the 82c88 instead of the processor in this con?guration, although their timing remains relatively the same. the hs-80c86rh status outputs ( s2, s1, and s0) provide type-of-cycle information and become 82c88 inputs. this bus cycle information speci?es read (code, data or i/o), write (data or i/o), interrupt acknowl- edge, or software halt. the 82c88 issues control signals specifying memory read or write, i/o read or write, or inter- rupt acknowledge. the 82c88 provides two types of write strobes, normal and advanced, to be applied as required. the normal write strobes have data valid at the leading edge of write. the advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. the transceiver receives the usual t and 0e inputs from the 82c88 dt/ r and den signals. for large multiple processor systems, the 82c89 bus arbiter must be added to the system to provide system bus man- agement. in this case, the pointer into the interrupt vector table, which is passed during the second int a cycle, can be derived from an hs-82c59arh located on either the local bus or the system bus. the processors int a output should drive the sysb/ resb input of the 82c89 to the proper state when reading the interrupt vector number from the hs- 82c59arh during the interrupt acknowledge sequence and software poll. a note on radiation hardened product availability there are no immediate plans to develop the 82c88 bus controller or the 82c89 arbiter as radiation hardened integrated circuits. a note on seu capability of the hs-80c86rh previous heavy ion testing of the hs-80c86rh has indi- cated that the seu threshold of this part is about 6 mev/mg/cm 2 . based upon these results and other analysis, a deep space galactic cosmic-ray environment will result in an seu rate of about 0.08 upsets/day.
874 spec number 518055 hs-80c86rh figure 6a. maximum mode hs-80c86rh typical configuration figure 6b. minimum mode hs-80c86rh typical configuration res gnd hs-82c85rh clock controller/ generator rdy bhe a16-a19 ad0-ad15 lock hs-80c86rh cpu s2 s1 s0 mn/ mx reset ready clk vdd c1 c2 gnd gnd 1 20 40 c1 = c2 = 0.1 m f gnd vdd clk s0 s1 s2 den dt/ r ale mrdc mwtc amwc iorc io wc aio wc int a 82c88 bus ctrlr stb oe 82c82 (2 or 3) t/ r oe hs-82c08rh transceiver (2) bhe nc nc addr data a0 e g hs-6617rh cmos prom (2) 2k x 8 2k x 8 cs rd wr cmos hs-82cxxrh peripherals hs-65262rh cmos ram (16) 16k x 1 w e gnd vdd nc addr/data wait state generator res gnd hs-82c85rh clock controller/ generator rdy bhe a16-a19 ad0-ad15 hs-80c86rh cpu mn/ mx reset ready clk vdd c1 c2 gnd 1 20 40 c1 = c2 = 0.1 m f vdd vdd bhe addr data a0 e g hs-6617rh cmos prom (2) 2k x 8 2k x 8 cs rd wr cmos hs-82cxxrh peripherals hs-65262rh cmos ram (16) 16k x 1 w e gnd vdd addr/data gnd m/ io int a rd wr dt/ r den ale optional for increased data bus drive wait state generator stb oe 82c82 (2 or 3) t/ r oe hs-82c08rh transceiver (2)
875 spec number 518055 hs-80c86rh waveforms figure 7. bus timing - minimum mode system notes: 1. all signals switch between voh and vol unless otherwise speci?ed. 2. rdy is sampled near the end of t2, t3, tw to determine if tw machines states are to be inserted. 3. two int a cycles run back-to-back. the hs-80c86rh local addr/data bus is inactive during both int a cycles. control signals are shown for the second int a cycle. 4. signals at hs-82c85rh are shown for reference only. 5. all timing measurements are made at 1.5v unless otherwise noted. t4 t3 t2 t1 tw tdvcl tcldx1 tcvctx twhdx tcvctx tchctv tclav tclaz tcvctv twlwh tchctv tcvctx tcvctv tclav tcldv tclax tcldx2 tcl2cl1 tcvctv data out ad15-ad0 invalid address clk (hs-82c85rh output) write cycle (note 1) ( rd, int a, dt/ r = voh) ad15-ad0 den wr int a cycle (notes 1, 3) ( rd, wr = voh bhe = vol) ad15-ad0 dt/ r int a den ad15-ad0 software halt - den, rd, wr, int a = voh dt/ r = indeterminate software halt tch1ch2 tcvctv pointer
876 spec number 518055 hs-80c86rh figure 8. bus timing - minimum mode system notes: 1. all signals switch between voh and vol unless otherwise speci?ed. 2. rdy is sampled near the end of t2, t3, tw to determine if tw machines states are to be inserted. 3. two int a cycles run back-to-back. the hs-80c86rh local addr/data bus is inactive during both int a cycles. control signals are shown for the second int a cycle. 4. signals at hs-82c85rh are shown for reference only. 5. all timing measurements are made at 1.5v unless otherwise noted. waveforms (continued) tclcl tw t1 t2 t3 t4 tchctv tchcl tclch tchctv tclav tavll tcldv tclax tclav tlhll tllax tchll tcllh tr1vcl tchryx vih vil trylcl tclrix tryhch tclaz tdvcl tcldx1 tazrl tclrh trhav trlrh tchctv tcvctx tcvctv tclrl tchctv clk (hs-82c85rh output) m/ io bhe/s7, a19/s6-a16/s3 ale rdy (hs-82c85rh input) see note 4 ready (hs-80c86rh input) read cycle (note 1) ( wr, int a = voh) ad15-ad0 rd dt/ r den tch1ch2 tcl2cl1 ad15-ad0 data in s7-s3 bhe, a19-a16
877 spec number 518055 hs-80c86rh figure 9. bus timing - maximum mode system notes: 1. all signals switch between voh and vol unless otherwise speci?ed. 2. rdy is sampled near the end of t2, t3, tw to determine if tw machines states are to be inserted. 3. cascade address is valid between first and second int a cycle. 4. two int a cycles run back-to-back. the hs-80c86rh local addr/data bus is inactive during both int a cycles. control for pointer ad- dress is shown for the second int a cycle. 5. signals at hs-82c85rh or 82c88 are shown for reference only. 6. the issuance of the 82c88 command and control signals ( mrdc, mwtc, amwc, iorc, io wc, aio wc, int a and den) lags the active high 82c88 cen. 7. all timing measurements are made at 1.5v unless otherwise noted. 8. status inactive in state just prior to t4. waveforms (continued) t1 t2 t3 t4 tclcl tch1ch2 tcl2cl1 tw tchcl tclch tchsv tclsh (see note 8) tcldv tclax tclav tclav bhe, a19-a16 tsvlh tcllh tr1vcl tchll trylcl tclr1x tclav tryhch tdvcl tcldx1 tclax ad15-ad0 data in tryhsh tclrh trhav tchdtl tclrl trlrh tchdth tazrl tclml tclmh tcvnv tcvnx tclaz clk qs0, qs1 s2, s1, s0 (except halt) bhe/s7, a19/s6-a16/s3 ale (82c88 output) rdy (hs-82c85rh input) note 5 ready (hs-80c86rh input) read cycle 82c88 outputs see notes 5, 6 mrdc or iorc den s7-s3 ad15-ad0 rd dt/ r tclav tchryx
878 spec number 518055 hs-80c86rh figure 10. bus timing - maximum mode system (using 82c88) notes: 1. all signals switch between voh and vol unless otherwise speci?ed. 2. rdy is sampled near the end of t2, t3, tw to determine if tw machines states are to be inserted. 3. cascade address is valid between first and second int a cycle. 4. two int a cycles run back-to-back. the hs-80c86rh local addr/data bus is inactive during both int a cycles. control for pointer ad- dress is shown for the second int a cycle. 5. signals at hs-82c85rh or 82c88 are shown for reference only. 6. the issuance of the 82c88 command and control signals ( mrdc, mwtc, amwc, iorc, io wc, aio wc, int a and den) lags the active high 82c88 cen. 7. all timing measurements are made at 1.5v unless otherwise noted. 8. status inactive in state just prior to t4. waveforms (continued) t1 t2 t3 t4 tw tclsh (see note 8) tcldx2 tcldv tclax tclav tclmh tdvcl tclml tchdth tclmh tcvnx tclav tchsv tclsh clk s2, s1, s0 (except halt) write cycle ad15-ad0 den amwc or aio wc mwtc or io wc 82c88 outputs see notes 5, 6 int a cycle ad15-ad0 (see notes 3, 4) ad15-ad0 mce/ pden dt/ r int a den 82c88 outputs see notes 5, 6 reserved for cascade addr tclaz tsvmch tclmch tcvnv software halt - rd, mrdc, iorc, mwtc, amwc, io wc, aio wc, int a, s0, s1 = voh tcvnv tclml tcvnx tclmh tcldx1 tclml tchsv pointer invalid address ad15-ad0 s2 tchdtl tclmcl
879 spec number 518055 hs-80c86rh figure 11. asynchronous signal recognition figure 12. bus lock signal timing (maximum mode only) figure 13. reset timing figure 14. request/grant sequence timing (maximum mode only) figure 15. hold/hold acknowledge timing (minimum mode only) waveforms (continued) nmi intr test clk signal tinvch (see note) note: setup requirements for asynchronous signals only to guarantee recognition at next clk. any clk cycle clk tclav lock tclav any clk cycle vcc clk reset 3 50 m s 3 4 clk cycles tcldx tdvcl clk tclgh rq/ gt previous grant ad15-ad0 rd, lock bhe/s7, a19/s6-a16/s3 s2, s1, s0 tclcl any clk cycle 3 0-clk cycles pulse 2 hs-80c86rh tgvch tchgx tclgl tclgh pulse 1 coprocessor rq tclaz hs-80c86rh gt pulse 3 coprocessor release (see note) tchsv tchsz note: the coprocessor may not drive the buses outside the region shown without risking contention. clk hold hlda ad15-ad0 bhe/s7, a19/s6-a16/s3 rd, wr, m/ io, dt/ r, den 80c86 thvch thvch tclhav 3 1clk 1 or 2 cycles tclaz coprocessor 80c86 tclhav cycle tchsz
880 spec number 518055 hs-80c86rh ac test circuit note: includes stray and jig capacitance. output from device under test test point cl (note) ac testing input, output waveform note: all inputs signals (other than clk) must switch between vil max -0.4v and vih min +0.4. clk must switch between 0.4v and vdd -0.4v. tr and tf must be less than or equal to 15ns. clk tr and tf must be less than or equal to 10ns. input vih vil - 0.4v output voh voh 1.5v 1.5v burn-in circuits hs-80c86rh 40 pin dip static hs-80c86rh 40 pin dip dynamic vdd = +6.5v 10% ta = +125 o c minimum part is static sensitive voltages must be ramped package: 40 lead dip resistors: 10k w 10% (pins 17, 18, 21-23, 31, 33) 2.7k w 5% (pins 2-16, 39) 1.0k w 5% 1/10w min (pin 19) minimum of 5 clk pulses after initial pulses, clk is left high pulses are 50% duty cycle square wave vdd = 6.5v 5% (burn-in) vdd = 6.0v 5% (life test) ta = +125 o c package: 40 lead dip part is static sensitive voltage must be ramped resistors: 10k w (pins 17, 18, 21, 22, 23, 33) 3.3k w (pins 2-16, 19, 30, 31, 39) 2.7k w loads as indicated all resistors are at least 1/8w, 10% f0 = 100khz, f1 = f0/2, f2 = f1/2 . . . reset, nmi low after initialization. ready pulsed low every 320ms mn/ mx changes state every 5.24s 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 clk vdd t t 3 5.0 m s 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 f15 f14 f13 f12 f10 f11 f8 f9 f5 f7 f6 f3 f4 f1 f2 nmi f0 load load load load load load load load load load load load reset f16 ready mn/ mx vdd load 2.7k w 2.7k w vdd
881 spec number 518055 hs-80c86rh hs-80c86rh 42 lead flatpack static hs-80c86rh 42 lead flatpack dynamic vdd = +6.5v 10% ta = +125 o c minimum part is static sensitive voltages must be ramped package: 42 lead flatpack resistors: 10k w 10% (pins 18, 19, 22-24, 32, 34) 2.7k w 5% (pins 2-16, 41) 1.0k w 5% 1/10w min (pin 20) minimum of 5 clk pulses after initial pulses, clk is left high pulses are 50% duty cycle square wave vdd = 6.5v 5% (burn-in) vdd = 6.0v 5% (life test) ta = +125 o c package: 42 lead flatpack part is static sensitive voltage must be ramped resistors: 10k w (pins 17, 18, 19, 22, 23, 24, 34) 3.3k w (pins 2-16, 20, 31, 32, 41) 2.7k w loads as indicated all resistors are at least 1/8w, 10% f0 = 100khz, f1 = f0/2, f2 = f1/2 . . . reset, nmi low after initialization. ready pulsed low every 320 m s mn/ mx changes state every 5.24s burn-in circuits (continued) clk 1 2 3 4 5 6 7 8 9 21 13 10 11 12 14 15 16 17 18 19 20 37 38 39 40 41 42 35 34 33 32 31 28 29 30 36 26 23 24 25 22 27 vdd vdd f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 nmi f0 open mn/ mx f16 load ready reset load load load load load load load load load load load open 1 2 3 4 5 6 7 8 9 13 11 12 14 15 16 17 18 19 20 21 10 35 36 37 38 39 40 41 42 33 32 31 26 27 28 29 30 23 24 25 22 34 vdd load 2.7k w 2.7k w
882 spec number 518055 hs-80c86rh timing diagrams ready timing as compared to f5 reset, nmi, and mn/ mx timing as compared to f14 and f16 f0 = 100khz, 50% duty cycle square wave. f1 = f0/2, f2 = f1/2 . . . f16 = f15/2. ready, reset, and nmi timing are as shown below: t = 10 m s. all signals have rise/fall time limits: 100ns < t-rise, t-fall < 500ns reset has a pulse width = 8t and occurs every two cycles of f16. nmi has a pulse width = 4t and occurs every two cycles of f16. mn/ mx is a 50% duty cycle square wave and changes every eight cycles of f16. irradiation circuit 4t f5 ready f14 reset f16 nmi pulse 33 34 35 36 37 38 40 32 31 30 29 24 25 26 27 28 21 22 23 13 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 39 clock reset vss vcc mn/mx hold hlda test ready reset nmi intr clk gnd 1 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 load load load load load load load r2 load load load load load load r2 r2 vdd r3 load 2.7k w 2.7k w r3 r3 r2 1. vdd = 5.0v 0.5v 2. r2 = 3.3k w , r3 = 47k w 3. pins tied to gnd: 1-18, 20, 23, 39 pins tied to vcc: 22, 31, 33, 40 pins with loads: 24-29, 30, 32, 34-38 pins brought out: 19 (clock), 21 (reset) 4. clock and reset should be brought out separately so they can be toggled before irradiation. 5. group e sample size is 2 die/wafer. notes:
883 spec number 518055 hs-80c86rh intersil space level product flow - q all lots - wafer lot acceptance (including sem) method 5007 each wafer - gamma radiation veri?cation, two samples/wafer, 0 rejects, method 1019 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a 100% temperature cycle - method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind - method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, method 1015, condition a or b, 72 hours minimum, 125 o c minimum 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% pda 1, method 5004 (note 1) 100% dynamic burn-in, condition d, 240 hours, +125 o c or equivalent per method 1015 100% interim electrical test 2 (t2) 100% delta calculation (t0-t2) 100% pda 2, method 5004 (note 2) 100% final electric test (t3) 100% fine/gross leak, method 1014 100% radiographic, method 2012 (note 3) 100% external visual, method 2009 sample - group a, method 5005 (note 4) sample - group b, method 5005 (note 5) sample - group d, method 5005 (notes 5, 6) 100% data package generation (note 6) notes: 1. modi?ed sem inspection, not compliant to mil-std-883, method 2018. this device does not meet the class s minimum metal step c ov- erage of 50%. the metal does meet the current density requirement of <2 e 5 a/cm 2 . data provided upon request. 2. failures from subgroups 1, 7 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% of the failures from subgroup 7. 3. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 4. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 5. group b and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should i nclude separate line items for group b test, group b samples, group d tests and group d samples. 6. group d generic data, as defined by mil-i-38535, is optional and will not be supplied unless required by the p.o. when requir ed, the p.o. should include separate line items for group d generic data. generic data is not guaranteed to be available and is therefo re not available in all cases. 7. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). wafer lot acceptance report (method 5007) to include reproductions of sem photos with percent of step coverage. ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? x-ray report and film, including penetrameter measurements. ? lot serial number sheet (good unit(s) serial number and lot number). ? variables data (all delta operations). data is identi?ed by serial number. data header includes lot number and date of test. ? group b and d attributes and/or generic data is included when required by p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of data book. the certi?cate of conformance is signed by an authorized quality representative.
884 spec number 518055 hs-80c86rh intersil space level product flow - 8 each wafer - gamma radiation veri?cation, 2 samples/wafer, 0 rejects, method 1019 100% die attach periodic - wire bond pull monitor, method 2011 periodic - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition b csi and/or gsi precap (note 5) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% external visual 100% initial electrical test 100% dynamic burn-in, condition d, 160 hours, +125 o c, or equivalent, per method 1015 100% interim electrical test 100% pda, method 5004 (note 1) 100% final electric test 100% fine/gross leak, method 1014 100% external visual, method 2009 sample - group a, method 5005 (note 2) sample - group b, method 5005 (note 3) sample - group c, method 5005 (notes 3, 4) sample - group d, method 5005 (notes 3, 4) 100% data package generation (note 6) csi and/or gsi final (note 5) notes: 1. failures from subgroups 1, 7 are used for calculating pda. the maximum allowable pda = 5%. 2. alternate group a testing may be performed as allowed by mil-std-883, method 5005 may be performed. 3. group b, c, and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. shou ld include separate line items for group b test, group c test, group c samples, group d test and group d samples. 4. group c and/or group d generic data, as defined by mil-i-38535, is optional and will not be supplied unless required by the p .o. when required, the p.o. should include separate line items for group d generic data. generic data is not guaranteed to be available and is therefore not available in all cases. 5. csi and /or gsi inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should include separate line items for csi precap inspection, csi final inspection, gsi precap inspection, and/or gsi final inspection. 6. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? screening, electrical, and group a attributes (screening attributes begins at initial electrical test). ? group b, c and d attributes and/or generic data is included when required by p.o. ? variables data (all delta operations) data is identi?ed by serial number. data header includes lot number and date of test. ? group b and d attributes and/or generic data is included when required by p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of data book. the certi?cate of conformance is signed by an authorized quality representative.
885 spec number 518055 hs-80c86rh metallization mask layout hs-80c86rh (1) gnd (2) ad14 (3) ad13 (4) ad12 (5) ad11 ad6 (10) ad5 (11) ad10 (6) ad9 (7) ad8 (8) ad7 (9) ad4 (12) ad3 (13) ad2 (14) ad1 (15) ad0 (16) gnd (20) nmi (17) intr (18) clk (19) reset (21) ready (22) test (23) qsi (21) qs0 (25) (35) a19/s6 (32 ) rd (30) rq/ gt1 (31) rq/ gt0 (33) mn/ mx (29) lock (28) s2 (27) s1 (26 ) s0 (36) a18/s5 (34 ) bhe/s7 (38) ad16 (39) ad15 (40) vcc (37) a17/s4 metallization topology die dimensions: 6370 m m x 7420 m m x 485 m m metallization: type: al/s thickness: 11k ? 2k ? glassivation: thickness: 8k ? 1k ? worst case current density: <2 x 10 5 a/cm 2
886 spec number 518055 hs-80c86rh instruction set summary mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 data transfer mov = move: register/memory to/from register 1 0 0 0 1 0 d w mod reg r/m immediate to register/memory 1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1 immediate to register 1 0 1 1 w reg data data if w 1 memory to accumulator 1 0 1 0 0 0 0 w addr-low addr-high accumulator to memory 1 0 1 0 0 0 1 w addr-low addr-high register/memory to segment register ?? 1 0 0 0 1 1 1 0 mod 0 reg r/m segment register to register/memory 1 0 0 0 1 1 0 0 mod 0 reg r/m push = push: register/memory 1 1 1 1 1 1 1 1 mod 1 1 0 r/m register 0 1 0 1 0 reg segment register 0 0 0 reg 1 1 0 pop = pop: register/memory 1 0 0 0 1 1 1 1 mod 0 0 0 r/m register 0 1 0 1 1 reg segment register 0 0 0 reg 1 1 1 xchg = exchange: register/memory with register 1 0 0 0 0 1 1 w mod reg r/m register with accumulator 1 0 0 1 0 reg in = input from: fixed port 1 1 1 0 0 1 0 w port variable port 1 1 1 0 1 1 0 w out = output to: fixed port 1 1 1 0 0 1 1 w port variable port 1 1 1 0 1 1 1 w xlat = translate byte to al 1 1 0 1 0 1 1 1 lea = load ea to register2 1 0 0 0 1 1 0 1 mod reg r/m lds = load pointer to ds 1 1 0 0 0 1 0 1 mod reg r/m les = load pointer to es 1 1 0 0 0 1 0 0 mod reg r/m lahf = load ah with flags 1 0 0 1 1 1 1 1 sahf = store ah into flags 1 0 0 1 1 1 1 0 pushf = push flags 1 0 0 1 1 1 0 0 popf = pop flags 1 0 0 1 1 1 0 1
887 spec number 518055 hs-80c86rh arithmetic add = add: register/memory with register to either 0 0 0 0 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01 immediate to accumulator 0 0 0 0 0 1 0 w data data if w = 1 adc = add with carry: register/memory with register to either 0 0 0 1 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01 immediate to accumulator 0 0 0 1 0 1 0 w data data if w = 1 inc = increment: register/memory 1 1 1 1 1 1 1 w mod 0 0 0 r/m register 0 1 0 0 0 reg aaa = ascll adjust for add 0 0 1 1 0 1 1 1 daa = decimal adjust for add 0 0 1 0 0 1 1 1 sub = subtract: register/memory and register to either 0 0 1 0 1 0 d w mod reg r/m immediate from register/memory 1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01 immediate from accumulator 0 0 1 0 1 1 0 w data data if w = 1 sbb = subtract with borrow register/memory and register to either 0 0 0 1 1 0 d w mod reg r/m immediate from register/memory 1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01 immediate from accumulator 0 0 0 1 1 1 0 w data data if w = 1 dec = decrement: register/memory 1 1 1 1 1 1 1 w mod 0 0 1 r/m register 0 1 0 0 1 reg neg = change sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m cmp = compare: register/memory and register 0 0 1 1 1 0 d w mod reg r/m immediate with register/memory 1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01 immediate with accumulator 0 0 1 1 1 1 0 w data data if w = 1 aas = ascll adjust for subtract 0 0 1 1 1 1 1 1 das = decimal adjust for subtract 0 0 1 0 1 1 1 1 mul = multiply (unsigned) 1 1 1 1 0 1 1 w mod 1 0 0 r/m imul = integer multiply (signed) 1 1 1 1 0 1 1 w mod 1 0 1 r/m aam = ascll adjust for multiply 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 dlv = divide (unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m idlv = integer divide (signed) 1 1 1 1 0 1 1 w mod 1 1 1 r/m aad = ascli adjust for divide 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 cbw = convert byte to word 1 0 0 1 1 0 0 0 cwd = convert word to double word 1 0 0 1 1 0 0 1 instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
888 spec number 518055 hs-80c86rh logic not = invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m shl/sal = shift logical/arithmetic left 1 1 0 1 0 0 v w mod 1 0 0 r/m shr = shift logical right 1 1 0 1 0 0 v w mod 1 0 1 r/m sar = shift arithmetic right 1 1 0 1 0 0 v w mod 1 1 1 r/m rol = rotate left 1 1 0 1 0 0 v w mod 0 0 0 r/m ror = rotate right 1 1 0 1 0 0 v w mod 0 0 1 r/m rcl = rotate through carry flag left 1 1 0 1 0 0 v w mod 0 1 0 r/m rcr = rotate through carry right 1 1 0 1 0 0 v w mod 0 1 1 r/m and = and: reg./memory and register to either 0 0 1 0 0 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1 immediate to accumulator 0 0 1 0 0 1 0 w data data if w = 1 test = and function to flags, no result: register/memory and register 1 0 0 0 0 1 0 w mod reg r/m immediate data and register/memory 1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1 immediate data and accumulator 1 0 1 0 1 0 0 w data data if w = 1 or = or: register/memory and register to either 0 0 0 0 1 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1 immediate to accumulator 0 0 0 0 1 1 0 w data data if w = 1 xor = exclusive or: register/memory and register to either 0 0 1 1 0 0 d w mod reg r/m immediate to register/memory 1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1 immediate to accumulator 0 0 1 1 0 1 0 w data data if w = 1 string manipulation rep = repeat 1 1 1 1 0 0 1 z movs = move byte/word 1 0 1 0 0 1 0 w cmps = compare byte/word 1 0 1 0 0 1 1 w scas = scan byte/word 1 0 1 0 1 1 1 w lods = load byte/word to al/ax 1 0 1 0 1 1 0 w stos = stor byte/word from al/a 1 0 1 0 1 0 1 w control transfer call = call: direct within segment 1 1 1 0 1 0 0 0 disp-low disp-high indirect within segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m direct intersegment 1 0 0 1 1 0 1 0 offset-low offset-high seg-low seg-high indirect intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
889 spec number 518055 hs-80c86rh jmp = unconditional jump: direct within segment 1 1 1 0 1 0 0 1 disp-low disp-high direct within segment-short 1 1 1 0 1 0 1 1 disp indirect within segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m direct intersegment 1 1 1 0 1 0 1 0 offset-low offset-high direct intersegment 1 1 1 0 1 0 1 0 offset-low offset-high seg-low seg-high indirect intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m ret = return from call: within segment 1 1 0 0 0 0 1 1 within seg adding lmmed to sp 1 1 0 0 0 0 1 0 data-low data-high intersegment 1 1 0 0 1 0 1 1 intersegment adding immediate to sp 1 1 0 0 1 0 1 0 data-low data-high je/jz = jump on equal/zero 0 1 1 1 0 1 0 0 disp jl/jnge = jump on less/not greater or equal 0 1 1 1 1 1 0 0 disp jle/jng = jump on less or equal/ not greater 0 1 1 1 1 1 1 0 disp jb/jnae = jump on below/not above or equal 0 1 1 1 0 0 1 0 disp jbe/jna = jump on below or equal/not above 0 1 1 1 0 1 1 0 disp jp/jpe = jump on parity/parity even 0 1 1 1 1 0 1 0 disp jo = jump on overtlow 0 1 1 1 0 0 0 0 disp js = jump on sign 0 1 1 1 1 0 0 0 disp jne/jnz = jump on not equal/not zero 0 1 1 1 0 1 0 1 disp jnl/jge = jump on not less/greater or equal 0 1 1 1 1 1 0 1 disp jnle/jg = jump on not less or equal/greater 0 1 1 1 1 1 1 1 disp jnb/jae = jump on not below/above or equal 0 1 1 1 0 0 1 1 disp jnbe/ja = jump on not below or equal/above 0 1 1 1 0 1 1 1 disp jnp/jpo = jump on not par/par odd 0 1 1 1 1 0 1 1 disp jno = jump on not over?ow 0 1 1 1 0 0 0 1 disp jns = jump on not sign 0 1 1 1 1 0 0 1 disp loop = loop cx times 1 1 1 0 0 0 1 0 disp loopz/loope = loop while zero/equal 1 1 1 0 0 0 0 1 disp loopnz/loopne = loop while not zero/equal 1 1 1 0 0 0 0 0 disp jcxz = jump on cx zero 1 1 1 0 0 0 1 1 disp int = interrupt type specified 1 1 0 0 1 1 0 1 type type 3 1 1 0 0 1 1 0 0 into = interrupt on over?ow 1 1 0 0 1 1 1 0 iret = interrupt return 1 1 0 0 1 1 1 1 instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
890 spec number 518055 hs-80c86rh processor control clc = clear carry 1 1 1 1 1 0 0 0 cmc = complement carry 1 1 1 1 0 1 0 1 stc = set carry 1 1 1 1 1 0 0 1 cld = clear direction 1 1 1 1 1 1 0 0 std = set direction 1 1 1 1 1 1 0 1 cll = clear interrupt 1 1 1 1 1 0 1 0 st = set interrupt 1 1 1 1 1 0 1 1 hlt = halt 1 1 1 1 0 1 0 0 wait = wait 1 0 0 1 1 0 1 1 esc = escape (to external device) 1 1 0 1 1 x x x mod x x x r/m lock = bus lock prefix 1 1 1 1 0 0 0 0 notes: al = 8-bit accumulator ax = 16-bit accumulator cx = count register ds= data segment es = extra segment above/below refers to unsigned value. greater = more positive; less = less positive (more negative) signed values if d = 1 then to reg; if d = 0 then from reg if w = 1 then word instruction; if w = 0 then byte instruction if mod = 11 then r/m is treated as a reg ?eld if mod = 00 then disp = o ? , disp-low and disp-high are absent if mod = 01 then disp = disp-low sign-extended 16-bits, disp-high is absent if mod = 10 then disp = disp-high:disp-low if r/m = 000 then ea = (bx) + (si) + disp if r/m = 001 then ea = (bx) + (di) + disp if r/m = 010 then ea = (bp) + (si) + disp if r/m = 011 then ea = (bp) + (di) + disp if r/m = 100 then ea = (si) + disp if r/m = 101 then ea = (di) + disp if r/m = 110 then ea = (bp) + disp ? if r/m = 111 then ea = (bx) + disp disp follows 2nd byte of instruction (before data if required) ? except if mod = 00 and r/m = 110 then ea = disp-high: disp-low. ?? mov cs, reg/memory not allowed. if s:w = 01 then 16 bits of immediate data form the operand. if s:w. = 11 then an immediate data byte is sign extended to form the 16-bit operand. if v = 0 then count = 1; if v = 1 then count in (cl) x = don't care z is used for string primitives for comparison with zf flag. segment override prefix 001 reg 11 0 reg is assigned according to the following table: 16-bit (w = 1) 8-bit (w = 0) segment 000 ax 000 al 00 es 001 cx 001 cl 01 cs 010 dx 010 dl 10 ss 011 bx 011 bl 11 ds 100 sp 100 ah 00 es 101 bp 101 ch 00 es 110 si 110 dh 00 es 111 di 111 bh 00 es instructions which reference the flag register file as a 16-bit object use the symbol flags to represent the file: flags = x:x:x:x:(of):(df):(if):(tf):(sf):(zf):x:(af):x:(pf):x:(cf) mnemonics intel, 1978 instruction set summary (continued) mnemonic and description instruction code 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
891 spec number 518055 hs-80c86rh d40.6 mil-std-1835 cdip2-t40 (d-5, configuration c) 40 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 2.096 - 53.24 4 e 0.510 0.620 12.95 15.75 4 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.070 0.38 1.78 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 a 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n40 408 rev. 0 4/94 notes: 1. index area: a notch or a pin one identi?cation mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identi?cation shall not be used as a pin one identi?cation mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2 +1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa c a - b m d s s ccc c a - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a ceramic dual-in-line metal seal packages (sbdip)
892 spec number 518055 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hs-80c86rh e e1 d s1 b q e2 a c 1 a a m c1 b1 (c) (b) section a-a base lead finish metal m e n l k42.a top brazed 42 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a - 0.100 - 2.54 - b 0.017 0.025 0.43 0.64 - b1 0.017 0.023 0.43 0.58 - c 0.007 0.013 0.18 0.33 - c1 0.007 0.010 0.18 0.25 - d 1.045 1.075 26.54 27.31 3 e 0.630 0.650 16.00 16.51 - e1 - 0.680 - 17.27 3 e2 0.530 0.550 13.46 13.97 - e 0.050 bsc 1.27 bsc 11 k----- l 0.320 0.350 8.13 8.89 - q 0.045 0.065 1.14 1.65 8 s1 0.000 - 0.00 - 6 m - 0.0015 - 0.04 - n42 42- rev. 0 6/17/94 ceramic metal seal flatpack packages (flatpack) notes: 1. index area: a notch or a pin one identi?cation mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identi?cation shall not be used as a pin one identi?cation mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identi?cation mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and ?nish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the ?nished lead surfaces, when solder dip or tin plate lead ?nish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead ?nish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. 11. the basic lead spacing is 0.050 inch (1.27mm) between center lines. each lead centerline shall be located within 0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (n) lead.

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